1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including a metal embedded into a dielectric material having a low permittivity to enhance device performance.
2. Description of the Related Art
In modern integrated circuits, minimum features sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip. In integrated circuits having minimum dimensions of approximately 0.35 μm, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 0.18 μm and less, it turns out, however, that the signal propagation delay is no longer determined by the field effect transistors, but is limited, owing to the increased package density of the circuits, by the close proximity of the interconnect lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to their reduced cross-sectional area. The parasitic RC time constants increased by the increased line-to-line capacitance and the higher line resistances may not easily be compensated for without the introduction of a new type of material for forming metallization layers.
Traditionally, metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities, it is being replaced by copper, which has a significantly lower electrical resistance, a higher thermal conductivity and a higher resistivity against electromigration. Although device characteristics may significantly improve by applying copper as the metallization metal, for devices having feature sizes of 0.13 μm and less, it turns out that, additionally, the well-established and well-known dielectric materials, silicon dioxide (k≈4.2) and silicon nitride (k>5), have to be replaced by so-called low-k dielectric materials in order to effectively reduce signal propagation delay by interconnect lines. The transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer, however, is associated with a plurality of issues that must be dealt with.
For example, copper may not be deposited in higher amounts in an efficient manner by well-established deposition methods, such as chemical vapor deposition. Additionally, copper may not be efficiently patterned by anisotropic etch processes and therefore the so-called damascene technique is employed in forming metallization layers including copper. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. In order to reliably fill the trenches and vias, a certain amount of “overfill” is required and necessitates the subsequent removal of the excess copper. For removing the excess copper and thereby additionally planarizing the surface of the metallization layer, chemical mechanical polishing (CMP) has proven to be a viable process technique, although the removal of one or more materials from a substrate surface at sufficiently high removal rates without unduly affecting underlying material layers is a quite complex task.
The situation becomes even more complicated when a low-k dielectric material is provided instead of the well-known silicon dioxide, since typically the properties of the low-k dielectric material significantly differ from those of the silicon dioxide, especially where the mechanical stability is concerned. Since copper readily diffuses in a plurality of dielectric materials, usually one or more barrier layers are provided prior to the deposition of the copper and these barrier layers have to be removed along with the copper to provide electrically insulated interconnect lines and vias. Typical barrier materials, such as tantalum and tantalum nitride, exhibit a significantly higher hardness than the copper so that, at least at a last step of the CMP process, respective process parameters are selected to obtain a sufficiently high removal rate, thereby, however, jeopardizing the underlying soft low-k dielectric material. Since a certain degree of overpolish is required to reliably insulate the individual trenches and lines from each other, a significant polish of the low-k dielectric layer and also of the copper may occur, especially when the removal rate varies across the substrate surface. The final trenches and vias may then exhibit an undesired resistance variation due to fluctuations in their cross-sectional areas, thereby requiring that the process margins be set correspondingly wider.
A further issue of patterning the low-k dielectric layer concerns the photolithography technique, as especially the damascene technique requires the formation of precisely registered trenches and vias over a low-k dielectric material, possibly including highly reflective copper regions. Consequently, an anti-reflective coating (ARC) is usually formed over the low-k dielectric material to minimize the back-reflection of light into a photoresist layer formed on the ARC layer.
With reference to FIGS. 1a-1c, a typical conventional process technique for patterning a low-k dielectric material will now be described. In FIG. 1a, a semiconductor structure 100 comprises a substrate 101 including a first dielectric layer 102 in which a plurality of narrow metal regions 103 and a wide metal region 104 are formed. The substrate 101 may include a plurality of circuit elements (not shown), some or all of which may be electrically connected to one or more of the metal regions 103 and 104. The metal region may be comprised of any appropriate material, such as aluminum, copper, tantalum, titanium, tungsten, and the like. The first dielectric layer 102 may be comprised of any appropriate insulating material and, in sophisticated integrated circuits, the first dielectric layer 102 may be comprised of a low-k dielectric material. An etch stop layer 105 is formed over the first dielectric layer 102 and the metal regions 103, 104, followed by a second dielectric layer 106 substantially comprised of a low-k dielectric material in which highly conductive interconnect lines and vias are to be formed. Appropriate low-k materials may include hydrogen-containing silicon oxycarbide (SiCOH), or other silicon-containing materials, such as SiLK. Other appropriate low-K materials are MSQ, HSQ and the like. An anti-reflective coating layer 107 is located above the second dielectric layer 106 and a resist mask 108 is formed on the anti-reflective coating layer 107. The resist mask 108 comprises openings 109 and 110, the dimensions of which substantially correspond to the dimensions of the lines and vias to be formed in the second dielectric layer 106.
A typical process for forming the semiconductor structure 100 as shown in FIG. 1a may comprise the following processes. After providing the substrate 101 with the first dielectric layer 102 and the metal regions 103, 104 formed therein, wherein the formation of the first dielectric layer 102 and the metal regions 103, 104 may include substantially the same process steps as will be described later on, the etch stop layer 105 is formed by, for example, chemical vapor deposition. Typically, the etch stop layer 105 is formed of a low-k material so as to not unduly compromise the overall characteristics of the finally obtained insulating layer. Appropriate materials are silicon carbide and nitrogen-doped silicon carbide. For less critical applications, the etch stop layer 105 may be comprised of silicon nitride and other dielectric materials having a relatively high k. Thereafter, the second dielectric layer 106 is formed by advanced deposition methods or by spin-on techniques, depending on the type of low-k material used. Irrespective of the method for forming the second dielectric layer 106, in general the mechanical properties significantly differ from those of a conventional dielectric material such as silicon dioxide. After the formation of the low-k dielectric layer 106, the anti-reflective coating layer 107 is formed, wherein the optical characteristics thereof are adjusted so as to minimize the back reflection for a given wave-length during a subsequent photolithography step. For example, the anti-reflective coating layer 107 may be comprised of silicon-rich oxynitride, the optical characteristics of which may be adjusted by controlling the amount of silicon incorporated into the layer 107 during the deposition, by providing a specified ratio of the precursor gases during the deposition of the layer 107 to achieve a specified refractive index and extinction coefficient. Additionally the thickness of the layer 107 is controlled to finally match the optical characteristics to the underlying material layers and to the photoresist used for forming the resist mask 108. A proper adaptation of the anti-reflective coating layer 107 is especially important during the formation of trenches and vias over the highly reflective metal regions 103, 104. Next, a layer of photoresist is formed on the anti-reflective coating layer 107, wherein a thickness and a composition of the photoresist is selected in conformity with the wavelength used for exposing the photoresist and the underlying anti-reflective coating layer 107. After exposure, the photoresist is then developed to form the resist mask 108 including the openings 109 and 110.
FIG. 1b schematically shows the semiconductor structure 100 in an advanced manufacturing stage. Openings 113 and 114 are formed in the etch stop layer 105, the second dielectric layer 106, and the anti-reflective coating layer 107 over the metal regions 103 and 104, respectively. A barrier layer 111, for example comprising tantalum and/or tantalum nitride, is formed on the anti-reflective coating layer 107 and within the openings 113 and 114. Furthermore, copper 112 is filled in the openings 113 and 114, wherein excess copper is also provided outside the openings 113 and 114.
Starting from the configuration of FIG. 1a, an anisotropic etch process is carried out to form the openings 113, 114 in the anti-reflective coating layer 107, the low-k dielectric layer 106, and the etch stop layer 105. Due to the very different characteristics of these layers, varying etch parameters may be selected to finally obtain the openings 113, 114. In particular, the etch stop layer 105 exhibits a significantly lower etch rate than the low-k dielectric layer 106 to reliably stop the etch process on and in the etch stop layer 105, which is then opened by a different etch process. After performing one or more cleaning steps, for example to clean the exposed metal surface of the regions 103, 104, the barrier layer 111 is deposited by advanced sputter deposition techniques, wherein, depending on the type of material of the layer 106 and the metal to be filled in the opening 113, 114, an appropriate composition of the barrier layer 111 is selected. In a silicon-based layer 106 with copper as the fill metal, a bi-layer of tantalum/tantalum nitride is frequently used as the barrier layer 111. Thereafter, when copper is used as metal, a copper seed layer (not shown) is sputter deposited on the barrier layer 111 and then the bulk copper is deposited by electrochemical techniques.
FIG. 1c schematically depicts the semiconductor structure 100 with a completed metallization layer 120 including the low-k dielectric layer 106 and the copper-filled trenches 113, 114. As previously noted, the excess copper of the layer 112, shown in FIG. 1b, is removed by CMP, wherein typically a multi-step process is performed to effectively remove the excess copper and planarize the surface of the structure 100. During the removal of the excess copper, the barrier layer 111 outside the trenches 113 and 114 is also removed in order to electrically insulate neighboring trenches from each other. Moreover, the anti-reflective coating layer 107, typically exhibiting a relatively high k value, is removed so as to not unduly compromise the low-k characteristics of the metallization layer 120. In removing the barrier layer 111 and the anti-reflective coating layer 107, a certain amount of the dielectric material of the layer 106 and of the copper in the trenches 113, 114 may also be removed, wherein the degree of overpolishing depends on the type of structure, its position on the substrate surface since the removal rate may vary across the substrate diameter, and the like. In FIG. 1c, the removal rate at the relatively closely spaced trenches 113 may be higher than at the substrate location in the vicinity of the isolated trench 114. Due to the reduced mechanical stability of the low-k dielectric layer 106, a significant variation of the layer thickness may occur due to erosion, as indicated by 121, which finally results in a corresponding variation of the line resistance of the trenches 113. As previously noted, incompletely removing the anti-reflective coating layer 107 is not a promising option since the relatively high k value may result in substantial variations in the parasitic RC time constants in regions with minimally removed anti-reflective coating layer 107.
It has therefore been proposed to provide a specific cap layer prior to the formation of the anti-reflective coating layer 107 that may protect the underlying low-k dielectric layer during the CMP process. The corresponding formation of an additional cap layer and an anti-reflective coating layer, however, adds additional complexity and cost.
In view of the above-identified problems, a need therefore exists for an improved technique in patterning a low-k dielectric material layer.